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siva
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Quote siva Replybullet Topic: VLSI Projects Topics
    Posted: 20-Jun-2011 at 12:36pm
DESIGN OF LOW POWER FIR FILTER.
DESIGN AND IMPLEMENTATION OF REED SOLOMON ENCODER IN HDL.
DESIGN AND IMPLEMENTATION OF REED SOLOMON DECODER IN HDL.
DESIGN OF   32-BIT PCI-X BUS INTERFACE IP CORE AND IMPLEMENTATION ON FPGA BOARD.
DESIGN AND IMPLEMENTATION OF RS-232 SYSTEM CONTROLLER.
DESIGN OF 16-BIT MICRO CONTROLLER.
DESIGN AND IMPLEMENTATION OF ATMEL AVR AT90S1200 STANDARD RISC MICRO CONTROLLER.
DESIGN OF TIME SLOT INTERCHANGE DIGITAL SWITCH.
IMPLEMENTATION OF CYCLIC REDUNDANCY CHECKER FOR ERROR DETECTION AND CORRECTION.
DESIGN OF 8-BIT 2-DIMENTIONAL DISCRETE COSINE TRANSFORM.
IMPLEMENTATION OF FM RECEIVER TO DEMODULATE SQUARE WAVE SIGNAL MODULATED   IN FM.
DESIGN OF HIGH SPEED XMATCHPRO LOSSLESS DATA COMPRESSOR.
DESIGN AND IMPLEMENTATION OF MEMORY CONTROLLER IP CORE.
A VLSI PROGRESSIVE CODING FOR WAVELET BASED IMAGE COMPRESSION
DIGITAL DESIGN OF DS- CDMA TRANSMITTER USING VHDL AND FPGA
RTL SIMULATION OF QPSK MODEM
HIGH SPEED DDR- SDRAM CONTROLLER WITH 64-BIT DATA TRANSFER.
REDUNDANT RADIX – 4 CO-PROCESSOR FOR HIGH SPEED ARITHMETIC OPERATIONS.
IMPLEMENTATION OF PHELIX FOR FAST ENCRYPTION & AUTHENTICATION.
DESIGN & IMPLEMENTATION OF ATM KNOCK OUT SWITCH USING CONCENTRATOR.
SDR – SDRAM CONTROLLER WITH 64 - BIT DATA TRANSFER.
IMPLEMENTATION OF JPEG BASE LINE IMAGE COMPRESSION.
IMPLEMENTATION OF 8 – BIT PICO PROCESSOR TO PERFORM ARITHMETIC & LOGICAL OPERATIONS.
DESIGN OF ETHERNET IP   CORE 802.3 AND IMPLEMENTATION.
IMPLEMENTATION OF UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART–16550H)SERIES.
IMPLEMENTATION OF ON RAIL - PASSENGER INFORMATION SYSTEM USING VHDL.
RTL DESIGN & VERIFICATION OF AN 8 – BIT MICRO CONTROLLER.
IMPLEMENTATION OF DES ALGORITHM FOR DATA ENCRYPTION.
IMPLEMENTATION OF CONTROLLER AREA NETWORK (CAN) PROTOCOL.
DESIGN OF I2C BUS INTERFACE FOR PARALLEL TO SERIAL DATA TRANSFER.
IMPLEMENTATION OF FLOATING POINT MULTIPLIER FOR IEEE –754 BIT FORMAT.
DESIGN AND IMPLEMENTATION OF ALU IN HDL.
DESIGN OF FLOATING POINT ADDER FOR IEEE –754 BIT FORMAT.
DESIGN AND IMPLEMENTATION OF 64 POINT FFT / IFFT FOR IEEE 802.11A.
DESIGN AND IMPLEMENTATION OF FLOATING POINT UNIT WITH IEEE –754 BIT FORMAT.


 
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siva
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Quote siva Replybullet Posted: 01-Aug-2011 at 2:48pm
Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic---IEEE 2008.


A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture---IEEE 2009.


Designing Efficient Online Testable Reversible Adders with New Reversible Gate---IEEE 2007.


Deviation-Based LFSR Reseeding for Test-Data Compression---IEEE 2009.


Hardware implementation of Variable Precision Multiplication on FPGA---IEEE 2009.


Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension---IEEE 2009.


Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST---IEEE 2009.


Spread Spectrum Image Watermarking with Digital Design---IEEE 2009.


Superscalar Power Efficient Fast Fourier Transform FFT Architecture


The Design and FPGA Implementation of GF (2128 ) Multiplier for Ghash---IEEE 2009.


VLSI Design of Diminished-One Modulo 2n + 1 Adder Using Circular Carry Selection---IEEE 2009.


Left to Right Serial Multiplier for Large Numbers on FPGA.


A Compact AES Encryption Core on Xilinx FPGA.


A Novel Multiplexer based truncated array multiplier.


Design and Implementation of a Field Programmable CRC Circuit Architecture---IEEE 2009.


Exploiting Memory Soft Redundancy for Joint Improvement of Error Tolerance and Access Efficiency---IEEE 2009.


Soft-Error Tolerance and Mitigation in Asynchronous Burst-Mode Circuits---IEEE 2009.


Design of Network-on-Chip Architectures with a Genetic Algorithm-Based Technique---IEEE 2009.


Efficient On-Chip Crosstalk Avoidance CODEC Design---IEEE 2009.


Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits---IEEE 2009.


Fault Secure Encoder and Decoder for Memory Applications---IEEE 2007.


A Fast VLSI Design of SMS4 Cipher Based on Twisted BDD S-Box Architecture---IEEE 2009.


A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System---IEEE 2008.


A Generalization of a Fast RNS Conversion for a New 4-Modulus Base---IEEE 2009.


A VLSI Progressive Coding for Wavelet-based Image Compression---IEEE 2007.


A New Low Power Test Pattern Generator Using a Variable-Length Ring Counter---IEEE 2009.


A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations---IEEE 2009.


FPGA Implementation of Viterbi Decoder

 
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