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siva
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Quote siva Replybullet Topic: IEEE VLSI Project Topics
    Posted: 31-Jul-2011 at 9:59pm
IEEE 2011 Topics:

    An Efficient Implementation of Floating Point Multiplier
    A Distributed Canny Edge Detector And Its Implementation on FPGA
    A blind digital watermarking algorithm based on wavelet transform
    Design and Simulation of UART Serial Communication Module Based on VHDL
    Design and VLSI implementation of high-performance face-detection engine for mobile applications
    Design and Implementation of Area-optimized AES based on FPGA
    Design of Low Power And High Speed Configurable Booth Multiplier
    Digital watermarking using Bidimensional Empirical Mode Decomposition
    Face detection and recognition method based on skin color and depth information
    High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics
    A New Reversible Design of BCD Adder
    Design and Implementation of Low Power Digital FIR Filter based on low power multipliers and adders on xilinx FPGA
    A Very Fast and Low Power Carry Select Adder Circuit
    Feature Extraction of Digital Aerial Images by FPGA based implementation of edge detection algorithms
    An Implementation of a 2D FIR Filter Using the Signed-Digit Number System
    Design and Characterization of Parallel Prefix Adders using FPGAs
    FPGA based FFT Algorithm Implementation in WiMAX Communications System
    FPGA Design of AES Core Architecture for Portable Hard Disk
    FPGA Implementation of RS232 to Universal serial bus converter
    Image Encryption Based On AES Key Expansion

 
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siva
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Quote siva Replybullet Posted: 31-Jul-2011 at 9:59pm
IEEE 2010 Topics:

    Image Compression with Different Types of Wavelets
    Performance Efficient FPGA Implementation of Parallel 2-D MRI Image Filtering Algorithms using Xilinx System Generator
    VLSI Implementation of Autocorrelator and CORDIC algorithm for OFDM based WLAN
    Improvisation of Gabor Filter design using Verilog HDL
    Design of Low-Cost High-performance Floating-point Fused Multiply-Add with Reduced Power
    Image Edge Detection Based on FPGA
    A High-speed 32-bit Signed/Unsigned Pipelined Multiplier
    A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm
    FPGA Implementations of the Hummingbird Cryptographic Algorithm
    FPGA Implementation(s) of a Scalable Encryption Algorithm
    A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC
    Contrast Enhancement of Color Images using Tunable Sigmoid Function

 
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siva
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Quote siva Replybullet Posted: 31-Jul-2011 at 10:00pm
IEEE 2009 Topics:

    Fast Scaling in the Residue Number System
    VLSI Architecture and Chip for Combined Invisible Robust Watermarking
    Implementing Gabor Filter for Fingerprint Recognition Using Verilog HDL
    An Area-Efficient Universal Cryptography Processor for Smart Cards
    FPGA Based Power Efficient Channelizer for Software Defined Radio
    Improvement of the Orthogonal Code Convolution Capabilities Using FPGA Implementation
    The CSI Multimedia Architecture
    Design and Implementation of Boundary-Scan Circuit for FPGA
    Hardware Algorithm for Variable Precision Multiplication on FPGA
    VLSI Implementations of the Cryptographic Hash Functions MD6 and ïrRUPT
    VLSI Implementation of an Edge-Oriented Image Scaling Processor
    FPGA-Based Face Detection System Using Haar Classifiers
    An Effective Fast and Small-Area Parallel-Pipeline Architecture for OTM-Convolutional Encoders
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siva
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Quote siva Replybullet Posted: 31-Jul-2011 at 10:01pm
IEEE 2008 Topics:

    FPGA Implementation Of Usb Transceiver Macrocell Interface With USB2.0 Specifications
    Multiplier design based on ancient Indian Vedic Mathematics
    A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems
    Design Exploration of a Spurious Power Suppression Technique (SPST) and Its Applications
    Implementation of IEEE 802.11 a WLAN Baseband Processor
    Fuzzy based PID Controller using VHDL for Transportation Application Research on Fast Super-resolution Image Reconstruction Based on Image Sequence
    A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance
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siva
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Quote siva Replybullet Posted: 31-Jul-2011 at 10:02pm
IEEE 2007 Topics:

    A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth MultiplierLow-power and high-quality Cordic-based Loeffler DCT for signal processing
    Implementation of a Multi-channel UART Controller Based on FIFO Technique and FPGA
    A Low-Power Multiplier With the Spurious Power Suppression Technique
    FPGA Implementation(s) of a Scalable Encryption Algorithm
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siva
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Quote siva Replybullet Posted: 31-Jul-2011 at 10:06pm
Old IEEE Topics:

    A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design (Corrected)-2005
    A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture-2006
    An FPGA-based Architecture for Real Time Image Feature Extraction-2004
    Image Compression with Different Types of Wavelets-2006
    DCT-Based Image Watermarking Using Subsampling-2003
    Shift Invert Coding (SINV) for Low Power VLSI-2004
    Robust DWT-SVD Domain Image Watermarking: Embedding Data in All Frequencies-2004
    Digital Design of DS-CDMA Transmitter Using VHDL and FPGA-2005
    Design of Edge Detection Systems
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Aruna
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Quote Aruna Replybullet Posted: 28-Jun-2012 at 6:47pm
VLSI Design - IEEE Projects

MPV1 Design and implementation of Error Detector and Corrector (EDAC) Unit using VHDL
MPV2 Design and implementation of different adders using VHDL
MPV3 FIFO design and implementation using VHDL
MPV4 Design and implementation of Linear feedback Shift register using VHDL
MPV5 Design and implementation of RAM and ROM using VHDL
MPV6 Design and Implementation of UART using VHDL
MPV7 Design and implementation of Carry Save Array Arithmetic Multiplier
MPV8 Design and implementation of Content Addressable Memory using VHDL
MPV9 Design and implementation of SPI (Serial Peripheral Interface) using VHDL
MPV10 Design and implementation of Seven Segment decoder and bi-directional shift register
MPV11 Design and implementation of Look Ahead Carry Generator using VHDL
MPV12 Prototyping of Embedded processor using VHDL
MPV13 Design and implementation of Sequence Detector using VHDL
MPV14 Design and implementation of Digital Code Converters using VHDL
MPV15 Design and implementation of Electronic Voting Machine design using VHDL
MPV16 Design and implementation of Baud rate Generator using VHDL
MPV17 Design and implementation of unsigned serial divider using VHDL
MPV18 Design and implementation of signed adder, subtractor using VHDL
MPV19 Design and implementation of ALU using VHDL
MPV20 VHDL Design of central processing unit (CPU)
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