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razurkude
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Quote razurkude Replybullet Topic: New innovative projects of VHDL
    Posted: 11-Feb-2013 at 11:15pm
New innovative projects of VHDL of max 5 family...

 
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kranthikumar
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Quote kranthikumar Replybullet Posted: 23-Jul-2013 at 12:24pm

 
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PrashanthS
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Quote PrashanthS Replybullet Posted: 23-Jul-2013 at 12:57pm
VHDL/Verilog Project Ideas

The followings are some suggestion of the project topics. You need to do the specification, the behavioral level modeling and verification using VHDL or Verilog, RTL design using VHDL or Verilog, gate-level synthesis, simulation and verification using Synopses, place and route to generate physical layout of your design using Cadence.

Programmable 16-Tap FIR Filter:

This project is to implement a programmable FIR filter. The user can control the number of taps, which is ranging from 2 to 16, and also be able to change their coefficients. The coefficients are represented as fixed point 8-bits 2’s complement numbers, and so are the data values. It is assumed that either or both of the coefficients and data are fractional numbers. The chip outputs the most significant 8 bits of the accumulation result.

In the case of positive or negative overflow, the chip outputs the largest positive number or the smallest negative number, respectively. It also provides two signals to indicate the presence of overflow and its direction. To achieve a better accuracy, the internal dynamic range of the accumulator is assumed to be 12 bits.

The chip should interface with the outside world through the use of hand shaking signals for loading coefficients and data, and writing the result out of the chip. The number of MAC (Multiply and Accumulate Unit) that you can use is equal to 4. You have to design the chip as low power as possible, i.e. when the number of taps required is smaller, power gating and clock gating techniques should be used to reduce the power consumption of the idle part of the system.

A CORDIC Processor:

Many modern digital signal processing algorithm require the evaluation of elementary mathematical functions, such as trigonometric, exponential and logarithm functions which cannot be evaluated efficiently with traditional Multiply-and-add based arithmetic units.

An alternative arithmetic computing algorithm known as CORDIC (Coordinate Rotation Digital Computer) has been used for these kind of computation. It is an iterative arithmetic algorithm by formulating the computation tasks as a rotation of a 2 *1 vector in various coordinate systems. By varying a few simple parameters, the same CORDIC processor is capable of iteratively evaluation the elementary mathematical functions using the same hardware within the same amount of time.

In this project, you are required to build a processor to implement the CORDIC functions. You need to demonstrate how to use your processor to implement the following functions:
i)     cosine
ii)    sine
iii)   log

Design a VLSI Architecture for Median Filter:

In many signal processing applications, median filtering is required to smoothen the noisy signal. To cater for very high throughput, VLSI hardware is required for real-time computation. Most of the median value computations are based on sorting and hence efficient sorting structure is required to perform the median filter.

In this project you will need to implement a system that takes 8-bit data serially and computes the median value in parallel and pipelined fashion out of a programmable window size.
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LokeshNash
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Quote LokeshNash Replybullet Posted: 23-Jul-2013 at 1:19pm
VHDL Coding Rules

Purpose of VHDL Coding Rules:
* Prevent harmful or unpractical ways of coding
* Introduce a common, clear appearance for VHDL
* Increase readability for reviewing purposes
* Not to restrict creativity in any way

Presentation at - http://www.cs.tut.fi/~ege/Misc/dcs_vhdl_coding_rules_es_v4_4.pdf
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LokeshNash
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Quote LokeshNash Replybullet Posted: 23-Jul-2013 at 2:05pm
Analysis of the MIPS 32-bit, Pipelined Processor using Synthesized VHDL

For large and complicated ASIC designs, it is difficult to read and understand the circuits based on schematic drawings alone; as a result, a hardware description language is much needed for a succinct, descriptive, and human-readable summarization of the circuit.

In this paper, we explore VHDL, a hardware description language popular in educational environment. Through the design of a 32-bits pipelined CPU as described in “Computer Organization and Design” by John L. Hennessy and David A. Patterson, we present several VHDL compilers, simulators, and synthesizers that are readily accessible for academic environments.

Download Analysis of the MIPS 32-bit, Pipelined Processor using Synthesized VHDL.pdf
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